1. Field of the Invention
This disclosure directs itself to a full wave rectifier for use in the detection of differential data signals and to a differential signal detector including a pair of differential inputs and that single full wave rectifier coupled to the pair of differential inputs for detecting both high and low envelopes of signals at the pair of differential inputs and providing a sense signal at an output thereof. In particular, the disclosure directs itself to a full wave rectifier circuit having first and second differential input circuits. Each of the input circuits including a pair of field effect transistors of different conductivity type and having source terminals coupled together. More in particular, this disclosure directs itself to a differential signal detector having both a full wave rectifier and a voltage reference source with a common circuit configuration. The circuit configuration of both the full wave rectifier and the voltage reference source include first and second differential input circuits, each including a pair of field effect transistors of different conductivity type having respective source terminals coupled together.
2. Prior Art
High speed serial data communication is widely used using differential inputs to provide noise immunity. Contemporary systems require low power dissipation in combination with high performance. One way power is saved is through the use of a “sleep mode” where portions of the system are idle or shutdown when not needed. At the receiving end of a high speed differential signaling system, there are a number of circuits that can be idled when no signal is present on the data lines. Thus, such systems employ a signal detection circuit to signal the presence of data on the differential data lines.
A prior art signal detection circuit 100, illustrated in FIG. 1, includes a full wave rectifier circuit 20 to detect envelopes of signals at the pair of differential inputs. However, the prior art rectifier 20 does not have high immunity to common mode voltage signals. Accordingly, a preamplifier 10 in employed to provide the common mode voltage immunity lacking in the rectifier 20.
Preamplifier 10 is connected to the differential data input terminals 202 and 204 and couples the differential data signals RXa and RXb to the rectifier 20 on the coupling lines 6 and 8. The rectifier 20 responds to the input data with the output of a VSENSE signal output at the output terminal 22. The VSENSE signal is coupled to an input terminal 34 of a comparator 30. The comparator 30 compares the VSENSE signal with a reference voltage (VREF) input to terminal 32 of the comparator 30. If the voltage VSENSE signal exceeds VREF voltage, then a signal data detection signal is output at the output terminal 36 of comparator 30.
The preamplifier 10 required by system 100 must operate at the data rate of the high speed differential data, which in turn requires considerable power dissipation in a device that must be continuously active. Thus, there is a need for a signal detector employing a full wave rectifier with sufficiently high common mode noise immunity to obviate the need for a preamplifier in the differential data signal detector.